Multi-layered circuit boards are typically fabricated from layers of distinct circuit patterns separated by insulating material such as thin dielectric layers and interconnected by vias, or holes, that are drilled through the circuit board and plated with metal. It is desirable to interconnect integrated circuit packages and discrete electronic devices in highly dense assemblies to reduce signal paths and overall size.
However, the number of layers comprising multi-layered circuit boards becomes limited due to the increased non-uniformity in thickness and high fluid flow as more layers are added. During the processing of some exemplary circuit boards, layers of liquid crystalline polymer with copper on both sides are stacked up and then laminated together using a mechanical/electrical press, a mechanical hot oil press, or a mechanical hot steam press. Vias are then made by drilling holes in the multi-layered board and the interior surface of the vias are plated with metal to connect the distinct circuit patterns of the different layers. When the multilayer stack produces more liquid when being pressed into a laminated package, features or circuit tracers can shift and, as a result, not line up. In addition, when pressure and heat are applied to the multi-layer stack by the mechanical/electrical press, more pressure gets applied to the center of the multi-layer stack than the outer perimeter of the stack. This non-uniform pressure distribution results in a multi-layer stack having a non-uniform thickness and conductor layer feature shifting. In addition, it becomes difficult to drill and plate the interior surfaces of the vias within the non-uniformity of the multi-layer stack. This non-uniformity also becomes a performance issue at high frequencies.
Controlling or limiting the pressure applied to the multi-layer stack during the lamination cycle would decrease shifting of the layer features and would enable the production of a multi-layer stack having a precise uniform thickness. A multi-layer stack having reduced feature shifting and a uniform thickness enables more precise processing for the remaining processing steps including the creation of vias within the multi-layer stack having more uniform depths and diameters and, as a result, more uniform plating of the interior of the vias.
Current methods for fabricating multi-layer stacks of liquid crystalline polymers with copper foil are not capable of limiting feature shifting in the various layers and/or controlling or limiting the pressure applied to the multi-layer stacks during lamination. As a result, the number of layers that can be laminated to form a multi-layer circuit is limited in order to avoid feature shifting and non-uniformity in the thickness of the multi-layer stack.
Accordingly, there is a need for a method and apparatus for producing a high layer count, multi-layer circuit board having reduced feature shifting and a uniform thickness in order to provide a structure for supporting and interconnecting a high density of electronic devices.